On 2019/12/28 0:40, Martin Blumenstingl wrote:

Hi Hanjie,

overall this looks good to me and I have one question

On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin [off-list ref] wrote:
[...]

quoted

+       if (priv->soc_id == MESON_SOC_A1)
+               value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;

...here we have some CLK_SEL bit

[...]

quoted

-       priv->clk = devm_clk_get(dev, "xtal");
-       if (IS_ERR(priv->clk))
-               return PTR_ERR(priv->clk);
+       if (priv->soc_id == MESON_SOC_G12A) {
+               priv->clk = devm_clk_get(dev, "xtal");
+               if (IS_ERR(priv->clk))
+                       return PTR_ERR(priv->clk);
+       }

but here we don't need any parent/input clock?
does this mean that the USB2 PHY on the A1 SoC doesn't have any clock
inputs? how does it generate the correct clock for itself then?

Hi Martin

Actually, there is a "xtal_usb_phy" clock in A1 ctrl driver, it seems it's
better to be in the A1 phy driver.

I will move that clock here in next version.

Thanks,

Hanjie
 

Martin

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