Quoting Leonard Crestez (2019-09-16 16:03:53)

On 2019-09-16 11:33 PM, Stephen Boyd wrote:

quoted

Quoting Leonard Crestez (2019-08-20 08:45:06)

quoted

Dram frequency changes required modifying these clocks outside the
control of clk framework. Mark them as CLK_GET_RATE_NOCACHE so that
rates are always read back from registers.

Why can't we control the clks from the clk framework? Please add that
information in the commit text here.

OK, I will update commit message and comments

These clocks are only modified for DRAM frequency switches during which 
DRAM is briefly inaccessible. The switch is performed with a SMC call to 
by TF-A which runs from a SRAM area. Upon returning to linux several 
clocks bits are modified and we need to update them.

For rate bits an easy solution is to just mark with 
CLK_GET_RATE_NOCACHE, muxes are handled explicitly.

Is there any reason to expose or control these clks from Linux then? It
might be easier to just make any children clks of the DRAM frequency clk
"root" clks and then ignore any frequency that they might have.
Similarly, because the SMC call is used to change the frequency, it may
be simpler to handle that completely outside of the clk framework (it
may already be this way in this patch series but I haven't read
everything here).

Linux code performing the SMC call is also part of this series:

     https://patchwork.kernel.org/patch/11104145/

quoted

quoted

Signed-off-by: Leonard Crestez <redacted>
---
  drivers/clk/imx/clk-imx8mm.c | 6 ++++--
  drivers/clk/imx/clk-imx8mn.c | 6 ++++--
  drivers/clk/imx/clk-imx8mq.c | 7 ++++---
  3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 4ead3ea2713c..6cac80550f43 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c

@@ -526,12 +526,14 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
         /* IPG */
         clks[IMX8MM_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
         clks[IMX8MM_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
  
         /* IP */
-       clks[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000);
-       clks[IMX8MM_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mm_dram_apb_sels, base + 0xa080);
+       clks[IMX8MM_CLK_DRAM_ALT] = __imx8m_clk_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000,
+                       CLK_GET_RATE_NOCACHE);
+       clks[IMX8MM_CLK_DRAM_APB] = __imx8m_clk_composite("dram_apb", imx8mm_dram_apb_sels, base + 0xa080,
+                       CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);

Also, add a comment to this effect about why it can't be done from the
clk framework wherever the CLK_GET_RATE_NOCACHE flag is set. Basically
this flag is a hack and is an example of something that we need to fix.

DRAM freq switch requires multiple clk changes to be performed 
atomically while DRAM itself is not accessible so it's not something to 
"fix".

Ok. Fix may be the wrong word.


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