On Wed, 2019-09-11 at 15:35 +0100, Catalin Marinas wrote:

On Wed, Sep 11, 2019 at 12:54:38PM +0200, Nicolas Saenz Julienne wrote:

quoted

On Mon, 2019-09-09 at 11:58 +0200, Nicolas Saenz Julienne wrote:

quoted

 /*
- * Return the maximum physical address for ZONE_DMA32 (DMA_BIT_MASK(32)).
It
- * currently assumes that for memory starting above 4G, 32-bit devices
will
- * use a DMA offset.
+ * Return the maximum physical address for a zone with a given address
size
+ * limit. It currently assumes that for memory starting above 4G, 32-bit
+ * devices will use a DMA offset.
  */
-static phys_addr_t __init max_zone_dma32_phys(void)
+static phys_addr_t __init max_zone_phys(unsigned int zone_bits)
 {
        phys_addr_t offset = memblock_start_of_DRAM() & GENMASK_ULL(63,
32);
-       return min(offset + (1ULL << 32), memblock_end_of_DRAM());
+       return min(offset + (1ULL << zone_bits), memblock_end_of_DRAM());
 }

while testing other code on top of this series on odd arm64 machines I found
an
issue: when memblock_start_of_DRAM() != 0, max_zone_phys() isn't taking into
account the offset to the beginning of memory. This doesn't matter with
zone_bits == 32 but it does when zone_bits == 30.

I thought about this but I confused myself and the only case I had in
mind was an AMD Seattle system with RAM starting at 4GB.

I found the issue on a Cavium ThunderX2 server. Oddly enough the memory starts
at 0x802f0000.

What we need from this function is that the lowest naturally aligned
2^30 RAM is covered by ZONE_DMA while the rest to 2^32 are ZONE_DMA32.
This assumed that devices only capable of 30-bit (or 32-bit), have the
top address bits hardwired to be able access the bottom of the memory
(and this would be expressed in DT as the DMA offset).

Ok, I was testing a fix I wrote under these assumptions...

I guess the fix here is to use GENMASK_ULL(63, zone_bits).

...but this is way cleaner than my solution. Thanks!

Regards,
Nicolas