Re: [PATCH v2 1/2] arm64: dts: imx8mq: Add MIPI D-PHY

Hi Abel,
On Mon, Jul 15, 2019 at 11:10:27AM +0000, Abel Vesa wrote:

On 19-07-15 12:43:05, Guido Günther wrote:

quoted

Add a node for the Mixel MIPI D-PHY, "disabled" by default.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Acked-by: Angus Ainslie (Purism) <redacted>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d09b808eff87..891ee7578c2d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi

@@ -728,6 +728,19 @@
 				status = "disabled";
 			};
 
+			dphy: dphy@30a00300 {
+				compatible = "fsl,imx8mq-mipi-dphy";
+				reg = <0x30a00300 0x100>;
+				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+				clock-names = "phy_ref";
+				assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <24000000>;

We have the following in the clk-imx8mq in the vendor tree:

	clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]);

This unbypasses the video pll 1. And then we also have this:

	/* config video_pll1 clock */
	clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]);
	clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999);

We don't have anything like this in our tree. This is our current clock
tree in that area which is setup by either the lcdif or dcss DT:

 osc_25m                             10       12        0    25000000          0     0  50000
    video_pll1_ref_sel                1        1        0    25000000          0     0  50000
       video_pll1_ref_div             1        1        0     5000000          0     0  50000
          video_pll1                  1        1        0   593999998          0     0  50000
             video_pll1_bypass        1        1        0   593999998          0     0  50000
                video_pll1_out        2        2        0   593999998          0     0  50000
                   dsi_phy_ref        1        1        0    23760000          0     0  50000

e.g. for lcdif we have:

	lcdif: lcdif@30320000 {
		...
		clock-names = "pix";
		assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
				  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
				  <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
				  <&clk IMX8MQ_VIDEO_PLL1>;
		assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
				  <&clk IMX8MQ_VIDEO_PLL1>,
				  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
		assigned-clock-rates = <0>, <0>, <0>, <594000000>;
		...
	};

Do we want to add this add for dphy and lcdif?
Cheers,
 -- Guido

But none of that is acceptable upstream since the clock provider should not
use clock consumer API.

So please update the assigned-clock* properties to something like this:
				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
						  <&clk IMX8MQ_CLK_DSI_PHY_REF>,
						  <&clk IMX8MQ_VIDEO_PLL1>;
				assigned-clock-parents = <&clk IMX8MQ_CLK_27M>,
							 <&clk IMX8MQ_VIDEO_PLL1>,
							 <&clk IMX8MQ_VIDEO_PLL1_OUT>
							 <0>;
				assigned-clock-rates = <0>,
						       <0>,
						       <24000000>,             
						       <593999999>;

I've written this without testing, so please do test it on your setup.

quoted

+				#phy-cells = <0>;
+				power-domains = <&pgc_mipi>;
+				status = "disabled";
+			};
+
 			i2c1: i2c@30a20000 {
 				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 				reg = <0x30a20000 0x10000>;
-- 
2.20.1

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