[PATCH 1/2] clk: imx8mm: rename lcdif pixel clock
From: Fancy Fang <hidden>
Date: 2019-07-09 07:18:03
Also in:
linux-clk, lkml
Subsystem:
common clk framework, nxp i.mx clock drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Abel Vesa, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Rename 'lcdif' pixel clock related names to 'disp' names, since: First, the lcdif pixel clock is not supplied to LCDIF controller directly, but to some LPCG clock in display mix. So rename it to 'disp' pixel clock is more accurate. Second, in the imx8mn CCM specification which is designed after imx8mm, this same pixel root clock name has been modified from 'LCDIF_PIXEL_CLK_ROOT' to 'DISPLAY_PIXEL_CLK_ROOT'. Signed-off-by: Fancy Fang <redacted> --- drivers/clk/imx/clk-imx8mm.c | 4 ++-- include/dt-bindings/clock/imx8mm-clock.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 6b8e75df994d..42f1227a4952 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c@@ -210,7 +210,7 @@ static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_p static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; -static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
@@ -535,7 +535,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) clks[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); clks[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); clks[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); - clks[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); + clks[IMX8MM_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mm_disp_pixel_sels, base + 0xa500); clks[IMX8MM_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mm_sai1_sels, base + 0xa580); clks[IMX8MM_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mm_sai2_sels, base + 0xa600); clks[IMX8MM_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mm_sai3_sels, base + 0xa680);
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 07e6c686f3ef..91ef77efebd9 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h@@ -119,7 +119,7 @@ #define IMX8MM_CLK_PCIE1_PHY 104 #define IMX8MM_CLK_PCIE1_AUX 105 #define IMX8MM_CLK_DC_PIXEL 106 -#define IMX8MM_CLK_LCDIF_PIXEL 107 +#define IMX8MM_CLK_DISP_PIXEL 107 #define IMX8MM_CLK_SAI1 108 #define IMX8MM_CLK_SAI2 109 #define IMX8MM_CLK_SAI3 110
--
2.17.1
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