[RFC PATCH 22/30] PCI: cadence: Configure pci_epc_features to align BAR addresses to 256 Bytes
From: Kishon Vijay Abraham I <hidden>
Date: 2019-06-04 13:19:05
Also in:
linux-devicetree, linux-omap, linux-pci, linux-rockchip, lkml
Subsystem:
pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers:
Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds
Cadence PCIe controller has BITS[7:0] of the Inbound Address Translation Units AXI address reserved for special purpose. In order to accommodate this constraint, BAR addresses should be aligned to 256 Byte addresses. Configure pci_epc_features to align BAR addresses to 256 Bytes here. Signed-off-by: Kishon Vijay Abraham I <redacted> --- drivers/pci/controller/pcie-cadence-ep.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 3dc1a896c1e6..25638af7c668 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c@@ -484,6 +484,7 @@ static const struct pci_epc_features cdns_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, .msix_capable = false, + .align = 256, }; static const struct pci_epc_features cdns_pcie_epc_vf_features = {
--
2.17.1
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