Hello Leigh,

On Tue, 29 Jan 2019 15:36:56 +0000
Leigh Brown [off-list ref] wrote:

quoted

Apologies, I use webmail.  I have attached two files with the results
from running lspci -vvv -xxx

Thanks, that was very useful. I believe the issue comes from the fact
that your PCIe device has prefetchable BARs, while none of the 5 PCIe
devices I have here has prefetchable BARs. The pci-mvebu driver doesn't
support such BARs, but the change to the common PCI bridge emulation
logic made the prefetchable memory base / limit register read-write
while they were read-only before.

To verify this hypothesis, could you apply the following patch (on top
of 4.20), and see if it solves the problem ? Thanks!

This is probably not the right/correct fix, but it will at least allow
to verify that the problem is understood correctly.

Thomas

diff --git a/drivers/pci/pci-bridge-emul.c 

b/drivers/pci/pci-bridge-emul.c
index 129738362d90..f99b80c19809 100644

--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c

@@ -142,11 +142,7 @@ const static struct pci_bridge_reg_behavior

pci_regs_behavior[] = {
        },

        [PCI_PREF_MEMORY_BASE / 4] = {
-               /* The high 12-bits of pref mem base/limit are RW */
-               .rw = GENMASK(31, 20) | GENMASK(15, 4),
-
-               /* The low four bits of pref mem base/limit are RO */
-               .ro = GENMASK(19, 16) | GENMASK(3, 0),
+               .ro = ~0,
        },

        [PCI_PREF_BASE_UPPER32 / 4] = {