From: Stefan Agner <stefan@agner.ch> Date: 2019-01-18 13:59:49
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
Specifying all four CPUs shows no aversive effects on i.MX 6Dual
SoCs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/imx6q.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
From: Stefan Agner <stefan@agner.ch> Date: 2019-01-18 13:59:53
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
Specifying all four CPUs shows no aversive effects on i.MX 6Solo
SoCs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/imx6dl-tx6s-8034.dts | 4 ++++
arch/arm/boot/dts/imx6dl-tx6s-8035.dts | 4 ++++
arch/arm/boot/dts/imx6dl.dtsi | 5 +++++
3 files changed, 13 insertions(+)
From: Lucas Stach <l.stach@pengutronix.de> Date: 2019-01-18 14:12:25
Am Freitag, den 18.01.2019, 14:59 +0100 schrieb Stefan Agner:
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
But then it isn't correct either AFAICS. On i.MX6 all the PMU IRQs are
ORed together into a single SPI, instead of each core dealing with its
own PPI. So pretending that there are more IRQs with affinity to each
core isn't the right thing to do, no?
Regards,
Lucas
quoted hunk
Specifying all four CPUs shows no aversive effects on i.MX 6Dual
SoCs.
From: Stefan Agner <stefan@agner.ch> Date: 2019-01-18 15:41:55
On 18.01.2019 15:12, Lucas Stach wrote:
Am Freitag, den 18.01.2019, 14:59 +0100 schrieb Stefan Agner:
quoted
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
But then it isn't correct either AFAICS. On i.MX6 all the PMU IRQs are
ORed together into a single SPI, instead of each core dealing with its
own PPI. So pretending that there are more IRQs with affinity to each
core isn't the right thing to do, no?
Oh I see, we only have a single interrupt in the i.MX 6 case.
I agree, this patches are wrong.
Hm, but why does hw perf then think it needs to guess? Doesn't seem hard
to guess right if there is only one choice...
We probably need to do something like this?
From: Stefan Agner <stefan@agner.ch> Date: 2019-01-21 09:40:04
[adding Will/Mark]
On 18.01.2019 16:41, Stefan Agner wrote:
quoted hunk
On 18.01.2019 15:12, Lucas Stach wrote:
quoted
Am Freitag, den 18.01.2019, 14:59 +0100 schrieb Stefan Agner:
quoted
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
But then it isn't correct either AFAICS. On i.MX6 all the PMU IRQs are
ORed together into a single SPI, instead of each core dealing with its
own PPI. So pretending that there are more IRQs with affinity to each
core isn't the right thing to do, no?
Oh I see, we only have a single interrupt in the i.MX 6 case.
I agree, this patches are wrong.
Hm, but why does hw perf then think it needs to guess? Doesn't seem hard
to guess right if there is only one choice...
We probably need to do something like this?
Yeah, I see, it was on Friday... if anything, it should be:
- if (nr_cpu_ids != 1 && !pmu_has_irq_affinity(pdev->dev.of_node))
{
+ if (nr_cpu_ids != 1 && num_irqs != 1 &&
+ !pmu_has_irq_affinity(pdev->dev.of_node)) {
However, I realized that arm_pmu_platform actually currently only
assigns the one IRQ to the first CPU. This leads to perf not working if
a process is scheduled on another CPU then the first.
I could reproduce this. PID 763 is a long running task.
root@colibri-imx6-05051054:~# taskset -p 0x1 763
pid 763's current affinity mask: 3
pid 763's new affinity mask: 1
root@colibri-imx6-05051054:~# perf stat -e cpu-cycles -p 763
^C
Performance counter stats for process id '763':
7581021 cpu-cycles
1.222248490 seconds time elapsed
root@colibri-imx6-05051054:~# taskset -p 0x2 763
pid 763's current affinity mask: 1
pid 763's new affinity mask: 2
root@colibri-imx6-05051054:~# perf stat -e cpu-cycles -p 763
^C
Performance counter stats for process id '763':
<not counted> cpu-cycles
(0.00%)
1.050253575 seconds time elapsed
I guess we need to tell the PMU driver that a single IRQ should be used
for all CPUs?
--
Stefan
quoted
Regards,
Lucas
quoted
Specifying all four CPUs shows no aversive effects on i.MX 6Dual
SoCs.