[PATCH v5 15/17] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI
From: Jagan Teki <jagan@amarulasolutions.com>
Date: 2018-12-10 16:18:20
Also in:
dri-devel, linux-clk, lkml
Subsystem:
arm/allwinner sunxi soc support, common clk framework, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Michael Turquette, Stephen Boyd, Linus Torvalds
Minimum PLL used for MIPI is 500MHz, as per manual, but lowering the min rate by 300MHz can result proper working nkms divider with the help of desired dclock rate from panel driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 181b599dc163..b623c8150b4f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c@@ -183,6 +183,7 @@ static struct ccu_nkm pll_mipi_clk = { .n = _SUNXI_CCU_MULT(8, 4), .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), .m = _SUNXI_CCU_DIV(0, 4), + .min_rate = 300000000, /* Actual rate is 500MHz */ .common = { .reg = 0x040, .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
--
2.18.0.321.gffc6fa0e3
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