[PATCH v3 21/25] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
From: jagan@amarulasolutions.com (Jagan Teki)
Date: 2018-10-26 14:46:14
Also in:
dri-devel, linux-clk, linux-devicetree, lkml
Subsystem:
arm/allwinner sunxi soc support, common clk framework, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Michael Turquette, Stephen Boyd, Linus Torvalds
Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz, but lowering the min rate by 300MHz can result proper working nkms divider with the help of desired dclock rate from panel driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v3: - collect Stephen Ack - add tested credit Changes for v2: - none drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 019d67bf97c4..5a3a5b821f8b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c@@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = { .n = _SUNXI_CCU_MULT(8, 4), .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), .m = _SUNXI_CCU_DIV(0, 4), + .min_rate = 300000000, /* Actual rate is 500MHz */ + .max_rate = 1400000000UL, .common = { .reg = 0x040, .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
--
2.18.0.321.gffc6fa0e3