? 2018?9?6? GMT+08:00 ??2:18:13, Jagan Teki [off-list ref] ??:

On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng [off-list ref] wrote:

quoted

From: Jagan Teki <jagan@amarulasolutions.com>

Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.

The HDMI controller/PHY pair is similar to the one on H3/H5.

Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the TCON1 HDMI one.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock

Why? it was there in previous versions.

Based on my experiments, the bit has no effect on A64, and the parent
is always PLL-VIDEO0.