Dne torek, 04. september 2018 ob 11:18:47 CEST je Chen-Yu Tsai napisal(a):

On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec [off-list ref] 

wrote:

quoted

Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
rate is 24MHz, intermediate result when calculating final rate easily
overflows 32 bit variable.

Because of that, introduce function for calculating clock rate which
uses 64 bit variable for intermediate result.

Signed-off-by: Jernej Skrabec <redacted>

The code looks good. The A80's Video PLLs are also affected by this.
The range for N on the A80 is 12 ~ 255.

Can you add fixes and stable tags?

Sure.

ChenYu