[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

On Thu, Sep 21, 2017 at 10:31:16AM +0200, Simon Horman wrote:

On Wed, Sep 20, 2017 at 01:05:07PM +0000, Chris Paterson wrote:

quoted

Hello Simon,

quoted

From: devicetree-owner at vger.kernel.org [mailto:devicetree-
owner at vger.kernel.org] On Behalf Of Simon Horman
Sent: 15 September 2017 09:12
To: Chris Paterson <redacted>

On Wed, Sep 13, 2017 at 06:05:36PM +0100, Chris Paterson wrote:

quoted

From: Fabrizio Castro <redacted>

Enable the SDHI1 controller on iWave RZ/G1E SoM.

Signed-off-by: Fabrizio Castro <redacted>
Signed-off-by: Chris Paterson <redacted>
---
This patch is based on renesas-devel-20170913-v4.13.


 arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi

b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index e306e7c..f7f9cef 100644

--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi

@@ -9,6 +9,7 @@
  */

 #include "r8a7745.dtsi"
+#include <dt-bindings/gpio/gpio.h>

 / {
 	compatible = "iwave,g22m", "renesas,r8a7745"; @@ -38,6 +39,12

@@

quoted

 		function = "mmc";
 	};

+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+
 	i2c3_pins: i2c3 {
 		groups = "i2c3_b";
 		function = "i2c3";

@@ -54,6 +61,16 @@
 	status = "okay";
 };

+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;

No wp-gpios property means this is a ?SD slot, right?

Correct

quoted

Do you have any plans to enable sdr-50 and sdr-104?
Is it not supported for some reason?

Nope (unless the hardware changes down the line).
Both vmmc and vqmmc are fixed to 3V3 on the iWave-E SOM module.

Thanks, got it.

Thanks for the clarification above, I have applied this patch.