[PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
From: matthias.bgg@gmail.com (Matthias Brugger)
Date: 2017-07-05 11:09:57
Also in:
linux-devicetree, linux-mediatek, linux-pwm, lkml
On 06/30/2017 08:05 AM, Zhi Mao wrote:
quoted hunk ↗ jump to hunk
In original code, the pwm output frequency is not correct when set bit<3>=1 to PWMCON register. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> --- drivers/pwm/pwm-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 5c11bc7..d08b5b3 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c@@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (clkdiv > 7) return -EINVAL; - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
Just for clarification, BIT(15) enables old PWM mode, which ignores CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and can be discarded. Am I correct? I took mt7623n datasheet for reference. Regards, Matthias
mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);