[PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks

On 03/21, Shawn Guo wrote:

From: Shawn Guo <redacted>

To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.

While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.

Signed-off-by: Shawn Guo <redacted>
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Applied to clk-next

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