2017-03-21 16:38 GMT+08:00 Shawn Guo [off-list ref]:

From: Shawn Guo <redacted>

The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field.  The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.

Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.

Signed-off-by: Shawn Guo <redacted>

Reviewed-by: Jun Nie <redacted>