[PATCH] arm64: Add DTS support for FSL's LS1012A SoC

-----Original Message-----
From: Harninder Rai
Sent: Tuesday, November 15, 2016 12:15 PM
To: 'Shawn Guo' <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org; robh+dt at kernel.org;
mark.rutland at arm.com; oss at buserror.net; Bhaskar U
[off-list ref]; linux-arm-kernel at lists.infradead.org
Subject: RE: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC

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 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb

It seems that the patch is not generated against mainline kernel.  We
do not have fsl-ls1046a-qds.dtb target in mainline kernel.

You already clarified in the following mail :)

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+
+	reg_1p8v: regulator at 0 {

Drop the unit-address from node name, and name it like regulator-1p8v.

Ok. Will take care in V2

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+
+&duart0 {

Please sort labeled nodes alphabetically.

Ok Sure

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+	status = "okay";
+};
+
+&sai2 {
+	status = "okay";
+};

<snip>

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+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+			     /* Physical Secure PPI */
+		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
+			     /* Physical Non-Secure PPI */
+			     <1 14 IRQ_TYPE_LEVEL_LOW>,
+			     /* Virtual PPI */
+			     <1 11 IRQ_TYPE_LEVEL_LOW>,
+			     /* Hypervisor PPI */
+			     <1 10 IRQ_TYPE_LEVEL_LOW>;

The following form should be easier for read.

		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure

PPI */

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			     <1 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-

Secure PPI */

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			     <1 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual PPI */
			     <1 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor PPI

*/

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Agreed. My bad. Will correct in v2

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+		scfg: scfg at 1570000 {
+			compatible = "fsl,ls1012a-scfg", "syscon";
+			reg = <0x0 0x1570000 0x0 0x10000>;
+			big-endian;
+		};

Please sort these nodes with unit-address in order of the address.

ok

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Shawn