On Sun, Nov 13, 2016 at 05:34:44PM +0800, Chen-Yu Tsai wrote:

quoted

+static struct ccu_nkmp pll_ve_clk = {
+       .enable         = BIT(31),
+       .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+       .k              = _SUNXI_CCU_MULT(4, 2),
+       .m              = _SUNXI_CCU_DIV(0, 2),
+       .p              = _SUNXI_CCU_DIV(16, 2),

Any chance we'll support the bypass switch on this one?

I'm not sure this will be useful to have it running at 24MHz.

quoted

+static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2, 0);

Maybe we should set CLK_IS_CRITICAL on this one as well... in case the
bootloader uses pll-periph for mbus, and none of the dram gates are enabled.

Ack.

quoted

+static SUNXI_CCU_GATE(hosc_clk,        "hosc", "osc24M", 0x050, BIT(0), 0);

Why the extra "hosc" clock here? You should probably just internalize "osc24M".

I'd prefer to model it as it is modelled in hardware: you have two
crystals, and then a gate within the CCU.

quoted

+static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
+                                           "pll-video0-2x", "pll-video1-2x" };
+static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
+                                      csi_parents, csi_table,
+                                      0x134, 0, 5, 24, 2, BIT(31), 0);

Do you know if CSI needs to change the module clock?

Apparently not.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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