Hi Morimoto-san,

On Fri, Jun 17, 2016 at 4:14 AM, Kuninori Morimoto
[off-list ref] wrote:

quoted

quoted

Right, I had forgotten about that.
Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)

it seems the RCAN clock can just be modeled as a fixed clock. However,
its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
using an integer divider. Morimoto-san, can you please ask for clarification?

OK.
Now, I asked to HW team about that.
Please wait.

RCAN divider is fixed for 1/49

PLL1 (= 1560MHz)
  -> 1/2 (= 780MHz)
    -> RCAN divider 1/49 (= 15.9183..MHz)

Is this clear for you ?

Thanks, that's exactly what we need to know.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds