Hello.

On 06/01/2016 03:57 AM, Simon Horman wrote:

quoted

The initial R8A7792 SoC device tree including 2 CPU cores, GIC, timer, SYSC,
and the required  clock descriptions.

Signed-off-by: Sergei Shtylyov <redacted>

This is rather large for an initial DTSI. Did you give any consideration
to splitting it up: e.g. only providing what is needed to get to a serial
console?

    Was done in the v2 patchset...

With regards to SMP. Have you checked to make sure CPU hotplug works
on all CPUs?

    How to test the CPU hotplug? I've now added the SMP support and made sure 
both CPUs are online and serve IRQs...

And that the system behaves sanely on suspend/resume.

    I'd be thankful if you told me how to test that. :-)

If it is not possible to verify this at this stage then I would recommend
only enabling one CPU at this stage.

    Had a hard time debugging SMP until I realized I'd removed CPU1 from the 
device tree. :-)

MBR, Sergei