[PATCH 0/7] dts: sunxi: Add sunxi NAND Flash Controller support

Hello,

This series adds the sunxi NAND Flash Controller nodes to dts.

The first 4 patches is Boris Brezillon's patches with dtsi changes.
The second 1 patch adds Hynix H27UBG8T2BTR-BC NAND chip definition.
The last 2 patches enables NAND on Marsboard A10 board and Wexler TAB7200
tablet.

Aleksei Mamlin (3):
  mtd: nand: Add Hynix H27UBG8T2BTR-BC to nand_ids table
  ARM: dts: sun4i: Enable NAND on Marsboard A10
  ARM: dts: sun7i: Enable NAND on Wexler TAB7200

Boris Brezillon (4):
  ARM: dts: sun4i: Add A10 NAND controller pin definitions
  ARM: dts: sun4i: Add NFC node to Allwinner A10 SoC
  ARM: dts: sun7i: Add A20 NAND controller pin definitions
  ARM: dts: sun7i: Add NFC node to Allwinner A20 SoC

 arch/arm/boot/dts/sun4i-a10-marsboard.dts      | 41 ++++++++++++
 arch/arm/boot/dts/sun4i-a10.dtsi               | 91 ++++++++++++++++++++++++++
 arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 41 ++++++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi               | 91 ++++++++++++++++++++++++++
 drivers/mtd/nand/nand_ids.c                    |  4 ++
 5 files changed, 268 insertions(+)

-- 
2.7.3

From: Boris Brezillon <redacted>

Add NAND Flash controller node definition to the A10 SoC.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 146a08db..22950d8 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi

@@ -747,6 +747,17 @@
 			#size-cells = <0>;
 		};
 
+		nfc: nand at 01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <37>;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		emac: ethernet at 01c0b000 {
 			compatible = "allwinner,sun4i-a10-emac";
 			reg = <0x01c0b000 0x1000>;

-- 
2.7.3

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.

Signed-off-by: Aleksei Mamlin <redacted>
---
 drivers/mtd/nand/nand_ids.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index ccc05f5..ccdc773 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c

@@ -52,6 +52,10 @@ struct nand_flash_dev nand_flash_ids[] = {
 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
 		  NAND_ECC_INFO(40, SZ_1K), 4 },
+	{"H27UBG8T2BTR-BC 32G 3.3V 8-bit",
+		{ .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
+		  SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+		  NAND_ECC_INFO(40, SZ_1K), 0 },
 
 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),

-- 
2.7.3

Enable the NFC and describe the NAND flash connected to this controller.

Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index 2f6b21a..42aff91 100644
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts

@@ -159,6 +159,47 @@
 	status = "okay";
 };
 
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
+	status = "okay";
+
+	nand at 0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+
+		nand-ecc-mode = "hw";
+		nand-on-flash-bbt;
+
+		boot0 at 0 {
+			label = "boot0";
+			reg = /bits/ 64 <0x0 0x200000>;
+		};
+
+		boot0-rescue at 200000 {
+			label = "boot0-rescue";
+			reg = /bits/ 64 <0x200000 0x200000>;
+		};
+
+		uboot at 400000 {
+			label = "uboot";
+			reg = /bits/ 64 <0x400000 0x200000>;
+		};
+
+		uboot-rescue at 600000 {
+			label = "uboot-rescue";
+			reg = /bits/ 64 <0x600000 0x200000>;
+		};
+
+		main at 800000 {
+			label = "main";
+			reg = /bits/ 64 <0x800000 0xff800000>;
+		};
+	};
+};
+
 &ohci0 {
 	status = "okay";
 };

-- 
2.7.3

Enable the NFC and describe the NAND flash connected to this controller.

Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun4i-a10-marsboard.dts | 41 +++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
index 8e50723..ea6e2d5 100644
--- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts

@@ -150,6 +150,47 @@
 	status = "okay";
 };
 
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
+	status = "okay";
+
+	nand at 0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+
+		nand-ecc-mode = "hw";
+		nand-on-flash-bbt;
+
+		boot0 at 0 {
+			label = "boot0";
+			reg = /bits/ 64 <0x0 0x200000>;
+		};
+
+		boot0-rescue at 200000 {
+			label = "boot0-rescue";
+			reg = /bits/ 64 <0x200000 0x200000>;
+		};
+
+		uboot at 400000 {
+			label = "uboot";
+			reg = /bits/ 64 <0x400000 0x200000>;
+		};
+
+		uboot-rescue at 600000 {
+			label = "uboot-rescue";
+			reg = /bits/ 64 <0x600000 0x200000>;
+		};
+
+		main at 800000 {
+			label = "main";
+			reg = /bits/ 64 <0x800000 0xff800000>;
+		};
+	};
+};
+
 &ohci0 {
 	status = "okay";
 };

-- 
2.7.3

From: Boris Brezillon <redacted>

Add NAND Flash controller node definition to the A20 SoC.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 915979f..e473570 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi

@@ -826,6 +826,17 @@
 			#size-cells = <0>;
 		};
 
+		nfc: nand at 01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <37>;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		emac: ethernet at 01c0b000 {
 			compatible = "allwinner,sun4i-a10-emac";
 			reg = <0x01c0b000 0x1000>;

-- 
2.7.3

From: Boris Brezillon <redacted>

Define the NAND controller pin configs.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82e28c3..915979f 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi

@@ -1328,6 +1328,86 @@
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
+
+			nand_pins_a: nand_base0 at 0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15", "PC16";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs0_pins_a: nand_cs at 0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs1_pins_a: nand_cs at 1 {
+				allwinner,pins = "PC3";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs2_pins_a: nand_cs at 2 {
+				allwinner,pins = "PC17";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs3_pins_a: nand_cs at 3 {
+				allwinner,pins = "PC18";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs4_pins_a: nand_cs at 4 {
+				allwinner,pins = "PC19";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs5_pins_a: nand_cs at 5 {
+				allwinner,pins = "PC20";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs6_pins_a: nand_cs at 6 {
+				allwinner,pins = "PC21";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs7_pins_a: nand_cs at 7 {
+				allwinner,pins = "PC22";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb0_pins_a: nand_rb at 0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb1_pins_a: nand_rb at 1 {
+				allwinner,pins = "PC7";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
 		timer at 01c20c00 {

-- 
2.7.3

From: Boris Brezillon <redacted>

Define the NAND controller pin configs.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index a9c3190..146a08db 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi

@@ -1144,6 +1144,86 @@
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
+
+			nand_pins_a: nand_base0 at 0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15", "PC16";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs0_pins_a: nand_cs at 0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs1_pins_a: nand_cs at 1 {
+				allwinner,pins = "PC3";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs2_pins_a: nand_cs at 2 {
+				allwinner,pins = "PC17";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs3_pins_a: nand_cs at 3 {
+				allwinner,pins = "PC18";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs4_pins_a: nand_cs at 4 {
+				allwinner,pins = "PC19";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs5_pins_a: nand_cs at 5 {
+				allwinner,pins = "PC20";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs6_pins_a: nand_cs at 6 {
+				allwinner,pins = "PC21";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs7_pins_a: nand_cs at 7 {
+				allwinner,pins = "PC22";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb0_pins_a: nand_rb at 0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb1_pins_a: nand_rb at 1 {
+				allwinner,pins = "PC7";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
 		timer at 01c20c00 {

-- 
2.7.3

On Mon,  6 Jun 2016 13:24:23 +0300
Aleksei Mamlin [off-list ref] wrote:

Enable the NFC and describe the NAND flash connected to this controller.

Signed-off-by: Aleksei Mamlin <redacted>

Reviewed-by: Boris Brezillon <redacted>

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

On Mon,  6 Jun 2016 13:24:24 +0300
Aleksei Mamlin [off-list ref] wrote:

Enable the NFC and describe the NAND flash connected to this controller.

Signed-off-by: Aleksei Mamlin <redacted>

Reviewed-by: Boris Brezillon <redacted>

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

On Mon,  6 Jun 2016 13:24:22 +0300
Aleksei Mamlin [off-list ref] wrote:

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.

Still hoping to get this series [1] merged in 4.8, but if that's
not the case, I'll apply your patch.

BTW, that would be great if you could test it on your platforms.

Regards,

Boris

[1]https://lkml.org/lkml/2016/5/27/264

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

On Mon, 6 Jun 2016 20:55:49 +0200
Boris Brezillon [off-list ref] wrote:

On Mon,  6 Jun 2016 13:24:22 +0300
Aleksei Mamlin [off-list ref] wrote:

quoted

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.

Still hoping to get this series [1] merged in 4.8, but if that's
not the case, I'll apply your patch.

BTW, that would be great if you could test it on your platforms.

It seems that Hynix-specific initialization code can't handle H27UBG8T2BTR-BC
chip:

[    0.886153] nand: Could not find valid ONFI parameter page; aborting
[    0.892665] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.899025] nand: Hynix 1c03000.nand
[    0.902596] nand: bus width 8 instead 16 bit
[    0.906858] nand: No NAND device found
[    0.910620] sunxi_nand 1c03000.nand: failed to init nand chips
[    0.916528] sunxi_nand: probe of 1c03000.nand failed with error -22

Regards,

Boris

[1]https://lkml.org/lkml/2016/5/27/264

quoted

Signed-off-by: Aleksei Mamlin <redacted>
---
 drivers/mtd/nand/nand_ids.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index ccc05f5..ccdc773 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c

@@ -52,6 +52,10 @@ struct nand_flash_dev nand_flash_ids[] = {
 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
 		  NAND_ECC_INFO(40, SZ_1K), 4 },
+	{"H27UBG8T2BTR-BC 32G 3.3V 8-bit",
+		{ .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
+		  SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+		  NAND_ECC_INFO(40, SZ_1K), 0 },
 
 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

-- 
Thanks and regards,
Aleksei Mamlin

On Mon, 6 Jun 2016 22:59:03 +0300
Aleksei Mamlin [off-list ref] wrote:

On Mon, 6 Jun 2016 20:55:49 +0200
Boris Brezillon [off-list ref] wrote:

quoted

On Mon,  6 Jun 2016 13:24:22 +0300
Aleksei Mamlin [off-list ref] wrote:
  

quoted

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.  

Still hoping to get this series [1] merged in 4.8, but if that's
not the case, I'll apply your patch.

BTW, that would be great if you could test it on your platforms.
  

It seems that Hynix-specific initialization code can't handle H27UBG8T2BTR-BC
chip:

[    0.886153] nand: Could not find valid ONFI parameter page; aborting
[    0.892665] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.899025] nand: Hynix 1c03000.nand
[    0.902596] nand: bus width 8 instead 16 bit
[    0.906858] nand: No NAND device found
[    0.910620] sunxi_nand 1c03000.nand: failed to init nand chips
[    0.916528] sunxi_nand: probe of 1c03000.nand failed with error -22

Can you try this patch? It should fix the problem [1].

[1]http://code.bulix.org/6hjww1-100494


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

On Mon, 6 Jun 2016 22:31:38 +0200
Boris Brezillon [off-list ref] wrote:

On Mon, 6 Jun 2016 22:59:03 +0300
Aleksei Mamlin [off-list ref] wrote:

quoted

On Mon, 6 Jun 2016 20:55:49 +0200
Boris Brezillon [off-list ref] wrote:

quoted

On Mon,  6 Jun 2016 13:24:22 +0300
Aleksei Mamlin [off-list ref] wrote:
  

quoted

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.  

Still hoping to get this series [1] merged in 4.8, but if that's
not the case, I'll apply your patch.

BTW, that would be great if you could test it on your platforms.
  

It seems that Hynix-specific initialization code can't handle H27UBG8T2BTR-BC
chip:

[    0.886153] nand: Could not find valid ONFI parameter page; aborting
[    0.892665] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.899025] nand: Hynix 1c03000.nand
[    0.902596] nand: bus width 8 instead 16 bit
[    0.906858] nand: No NAND device found
[    0.910620] sunxi_nand 1c03000.nand: failed to init nand chips
[    0.916528] sunxi_nand: probe of 1c03000.nand failed with error -22

Can you try this patch? It should fix the problem [1].

[1]http://code.bulix.org/6hjww1-100494

Yes, it fixes problem. What about ONFI parameter page? Should it be ignored?
[    0.886068] nand: Could not find valid ONFI parameter page; aborting
[    0.892571] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.898917] nand: Hynix NAND 4GiB 3,3V 8-bit
[    0.903198] nand: 4096 MiB, MLC, erase size: 2048 KiB, page size: 8192, OOB size: 640
[    0.911908] Bad block table found at page 524032, version 0x01
[    0.918534] Bad block table found at page 523776, version 0x01
[    0.972112] 5 ofpart partitions found on MTD device 1c03000.nand
[    0.978116] Creating 5 MTD partitions on "1c03000.nand":
[    0.983477] 0x000000000000-0x000000200000 : "boot0"
[    0.988803] 0x000000200000-0x000000400000 : "boot0-rescue"
[    0.994692] 0x000000400000-0x000000600000 : "uboot"
[    0.999944] 0x000000600000-0x000000800000 : "uboot-rescue"
[    1.005763] 0x000000800000-0x000100000000 : "main"

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

-- 
Thanks and regards,
Aleksei Mamlin

On Tue, 7 Jun 2016 00:06:45 +0300
Aleksei Mamlin [off-list ref] wrote:

On Mon, 6 Jun 2016 22:31:38 +0200
Boris Brezillon [off-list ref] wrote:

quoted

On Mon, 6 Jun 2016 22:59:03 +0300
Aleksei Mamlin [off-list ref] wrote:
  

quoted

On Mon, 6 Jun 2016 20:55:49 +0200
Boris Brezillon [off-list ref] wrote:
  

quoted

On Mon,  6 Jun 2016 13:24:22 +0300
Aleksei Mamlin [off-list ref] wrote:
    

quoted

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.    

Still hoping to get this series [1] merged in 4.8, but if that's
not the case, I'll apply your patch.

BTW, that would be great if you could test it on your platforms.
    

It seems that Hynix-specific initialization code can't handle H27UBG8T2BTR-BC
chip:

[    0.886153] nand: Could not find valid ONFI parameter page; aborting
[    0.892665] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.899025] nand: Hynix 1c03000.nand
[    0.902596] nand: bus width 8 instead 16 bit
[    0.906858] nand: No NAND device found
[    0.910620] sunxi_nand 1c03000.nand: failed to init nand chips
[    0.916528] sunxi_nand: probe of 1c03000.nand failed with error -22  

Can you try this patch? It should fix the problem [1].

[1]http://code.bulix.org/6hjww1-100494
  

Yes, it fixes problem. What about ONFI parameter page? Should it be ignored?

It should be ignored: your NAND is not 'ONFI compatible', the datasheet
just says that it supports the' ONFI command set', which is not the
same :).
The trace you're seeing here is just notifying that the core failed to
detect an ONFI NAND, which is expected in your case.

[    0.886068] nand: Could not find valid ONFI parameter page; aborting
[    0.892571] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.898917] nand: Hynix NAND 4GiB 3,3V 8-bit
[    0.903198] nand: 4096 MiB, MLC, erase size: 2048 KiB, page size: 8192, OOB size: 640
[    0.911908] Bad block table found at page 524032, version 0x01
[    0.918534] Bad block table found at page 523776, version 0x01
[    0.972112] 5 ofpart partitions found on MTD device 1c03000.nand
[    0.978116] Creating 5 MTD partitions on "1c03000.nand":
[    0.983477] 0x000000000000-0x000000200000 : "boot0"
[    0.988803] 0x000000200000-0x000000400000 : "boot0-rescue"
[    0.994692] 0x000000400000-0x000000600000 : "uboot"
[    0.999944] 0x000000600000-0x000000800000 : "uboot-rescue"
[    1.005763] 0x000000800000-0x000100000000 : "main"

quoted

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com  

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

On Mon, 6 Jun 2016 22:31:38 +0200
Boris Brezillon [off-list ref] wrote:

On Mon, 6 Jun 2016 22:59:03 +0300
Aleksei Mamlin [off-list ref] wrote:

quoted

On Mon, 6 Jun 2016 20:55:49 +0200
Boris Brezillon [off-list ref] wrote:
  

quoted

On Mon,  6 Jun 2016 13:24:22 +0300
Aleksei Mamlin [off-list ref] wrote:
    

quoted

Add the full description of the Hynix H27UBG8T2BTR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.    

Still hoping to get this series [1] merged in 4.8, but if that's
not the case, I'll apply your patch.

BTW, that would be great if you could test it on your platforms.
    

It seems that Hynix-specific initialization code can't handle H27UBG8T2BTR-BC
chip:

[    0.886153] nand: Could not find valid ONFI parameter page; aborting
[    0.892665] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xd7
[    0.899025] nand: Hynix 1c03000.nand
[    0.902596] nand: bus width 8 instead 16 bit
[    0.906858] nand: No NAND device found
[    0.910620] sunxi_nand 1c03000.nand: failed to init nand chips
[    0.916528] sunxi_nand: probe of 1c03000.nand failed with error -22  

Can you try this patch? It should fix the problem [1].

Brian, I have a question regarding the extended NAND ids (not full-ids)
defined in the nand_ids table. Are they really valid for all vendors?

If that's the case, why are we extracting the bus width from the id[3]
since we already have this information in the options field?

[1]http://code.bulix.org/6hjww1-100494

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

On Mon,  6 Jun 2016 13:24:21 +0300
Aleksei Mamlin [off-list ref] wrote:

Should be
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		emac: ethernet at 01c0b000 {
 			compatible = "allwinner,sun4i-a10-emac";
 			reg = <0x01c0b000 0x1000>;
-- 
2.7.3

-- 
Thanks and regards,
Aleksei Mamlin

Hi,

On Mon, Jun 06, 2016 at 01:24:24PM +0300, Aleksei Mamlin wrote:

This feels a bit premature. The two boards you're using have an MLC
NAND which is not supported yet. Until there's proper MLC support in
the kernel, I'm not sure we want to enable that for end-users when we
know that things will get wrong.

However, after discussing this with Boris, I appreciate that we don't
have any example available because of this policy for people that want
to opt-in anyway.

What we could do is to still mark the status as disabled in the DTS,
with a big fat warning as comment just before, so that it requires
user action, and that user will have been warned.

Would that work for you?
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Hi,

On Mon, Jun 06, 2016 at 01:24:18PM +0300, Aleksei Mamlin wrote:

We usually enable only the pin groups that are actually used by some
board to avoid bloating the DT too much.

And the nodes should be sorted alphabetically.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Thu, 9 Jun 2016 00:03:14 +0200
Maxime Ripard [off-list ref] wrote:

Hi,

On Mon, Jun 06, 2016 at 01:24:24PM +0300, Aleksei Mamlin wrote:

quoted

Enable the NFC and describe the NAND flash connected to this controller.

Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index 2f6b21a..42aff91 100644
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts

@@ -159,6 +159,47 @@
 	status = "okay";
 };
 
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
+	status = "okay";
+
+	nand at 0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+
+		nand-ecc-mode = "hw";
+		nand-on-flash-bbt;
+
+		boot0 at 0 {
+			label = "boot0";
+			reg = /bits/ 64 <0x0 0x200000>;
+		};
+
+		boot0-rescue at 200000 {
+			label = "boot0-rescue";
+			reg = /bits/ 64 <0x200000 0x200000>;
+		};
+
+		uboot at 400000 {
+			label = "uboot";
+			reg = /bits/ 64 <0x400000 0x200000>;
+		};
+
+		uboot-rescue at 600000 {
+			label = "uboot-rescue";
+			reg = /bits/ 64 <0x600000 0x200000>;
+		};
+
+		main at 800000 {
+			label = "main";
+			reg = /bits/ 64 <0x800000 0xff800000>;
+		};
+	};
+};

This feels a bit premature. The two boards you're using have an MLC
NAND which is not supported yet. Until there's proper MLC support in
the kernel, I'm not sure we want to enable that for end-users when we
know that things will get wrong.

However, after discussing this with Boris, I appreciate that we don't
have any example available because of this policy for people that want
to opt-in anyway.

What we could do is to still mark the status as disabled in the DTS,
with a big fat warning as comment just before, so that it requires
user action, and that user will have been warned.

Would that work for you?
Maxime

Let's drop this two patches with boards dts changes until we get proper MLC
support in kernel.

As for examples - I'll update linux-sunxi wiki with how to enable NAND 
controller and describe NAND chips in DTS. People who want to add NAND support 
to their boards will be warned that it is risky for now.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

-- 
Thanks and regards,
Aleksei Mamlin

On Thu, Jun 09, 2016 at 11:11:00AM +0300, Aleksei Mamlin wrote:

On Thu, 9 Jun 2016 00:03:14 +0200
Maxime Ripard [off-list ref] wrote:

quoted

Hi,

On Mon, Jun 06, 2016 at 01:24:24PM +0300, Aleksei Mamlin wrote:

quoted

Enable the NFC and describe the NAND flash connected to this controller.

Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index 2f6b21a..42aff91 100644
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts

@@ -159,6 +159,47 @@
 	status = "okay";
 };
 
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
+	status = "okay";
+
+	nand at 0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+
+		nand-ecc-mode = "hw";
+		nand-on-flash-bbt;
+
+		boot0 at 0 {
+			label = "boot0";
+			reg = /bits/ 64 <0x0 0x200000>;
+		};
+
+		boot0-rescue at 200000 {
+			label = "boot0-rescue";
+			reg = /bits/ 64 <0x200000 0x200000>;
+		};
+
+		uboot at 400000 {
+			label = "uboot";
+			reg = /bits/ 64 <0x400000 0x200000>;
+		};
+
+		uboot-rescue at 600000 {
+			label = "uboot-rescue";
+			reg = /bits/ 64 <0x600000 0x200000>;
+		};
+
+		main at 800000 {
+			label = "main";
+			reg = /bits/ 64 <0x800000 0xff800000>;
+		};
+	};
+};

This feels a bit premature. The two boards you're using have an MLC
NAND which is not supported yet. Until there's proper MLC support in
the kernel, I'm not sure we want to enable that for end-users when we
know that things will get wrong.

However, after discussing this with Boris, I appreciate that we don't
have any example available because of this policy for people that want
to opt-in anyway.

What we could do is to still mark the status as disabled in the DTS,
with a big fat warning as comment just before, so that it requires
user action, and that user will have been warned.

Would that work for you?
Maxime

Let's drop this two patches with boards dts changes until we get proper MLC
support in kernel.

As for examples - I'll update linux-sunxi wiki with how to enable NAND 
controller and describe NAND chips in DTS. People who want to add NAND support 
to their boards will be warned that it is risky for now.

That works for me too.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Hello,

This series adds the sunxi NAND Flash Controller pin definitions and nodes to
dts.

Changes since v1:
- Remove patch with Hynix H27UBG8T2BTR-BC MLC NAND chip definition.
- Remove patches with NAND support on Marsboard A10 board and Wexler TAB7200.
- Enable only the pin groups that are actually used by sunxi boards.
- Enable DMA support. Depends on sunxi NFC DMA support([1], [2]), merged into
  linux-nand.

[1] http://lists.infradead.org/pipermail/linux-mtd/2016-April/066899.html
[2] http://lists.infradead.org/pipermail/linux-mtd/2016-April/066898.html

Boris Brezillon (4):
  ARM: dts: sun4i: Add A10 NAND controller pin definitions
  ARM: dts: sun4i: Add NFC node to Allwinner A10 SoC
  ARM: dts: sun7i: Add A20 NAND controller pin definitions
  ARM: dts: sun7i: Add NFC node to Allwinner A20 SoC

 arch/arm/boot/dts/sun4i-a10.dtsi | 65 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi | 65 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 130 insertions(+)

-- 
2.7.3

From: Boris Brezillon <redacted>

Define the NAND controller pin configs.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index de4231e..ad984f8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi

@@ -1168,6 +1168,58 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			nand_pins_a: nand_base0 at 0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15", "PC16";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs0_pins_a: nand_cs at 0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs1_pins_a: nand_cs at 1 {
+				allwinner,pins = "PC3";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs2_pins_a: nand_cs at 2 {
+				allwinner,pins = "PC17";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs3_pins_a: nand_cs at 3 {
+				allwinner,pins = "PC18";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb0_pins_a: nand_rb at 0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb1_pins_a: nand_rb at 1 {
+				allwinner,pins = "PC7";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			ps20_pins_a: ps20 at 0 {
 				allwinner,pins = "PI20", "PI21";
 				allwinner,function = "ps2";

-- 
2.7.3

From: Boris Brezillon <redacted>

Add NAND Flash controller node definition to the A10 SoC.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e579bdd..308ed5d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi

@@ -719,6 +719,19 @@
 			#dma-cells = <2>;
 		};
 
+		nfc: nand at 01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <37>;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+			dma-names = "rxtx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		spi0: spi at 01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;

-- 
2.7.3

From: Boris Brezillon <redacted>

Add NAND Flash controller node definition to the A20 SoC.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index ad984f8..7d7560f 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi

@@ -798,6 +798,19 @@
 			#dma-cells = <2>;
 		};
 
+		nfc: nand at 01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+			dma-names = "rxtx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		spi0: spi at 01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;

-- 
2.7.3

From: Boris Brezillon <redacted>

Define the NAND controller pin configs.

Signed-off-by: Boris Brezillon <redacted>
Signed-off-by: Aleksei Mamlin <redacted>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 6d9c7c70..e579bdd 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi

@@ -1033,6 +1033,58 @@
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
 
+			nand_pins_a: nand_base0 at 0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15", "PC16";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs0_pins_a: nand_cs at 0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs1_pins_a: nand_cs at 1 {
+				allwinner,pins = "PC3";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs2_pins_a: nand_cs at 2 {
+				allwinner,pins = "PC17";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_cs3_pins_a: nand_cs at 3 {
+				allwinner,pins = "PC18";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb0_pins_a: nand_rb at 0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			nand_rb1_pins_a: nand_rb at 1 {
+				allwinner,pins = "PC7";
+				allwinner,function = "nand0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			ps20_pins_a: ps20 at 0 {
 				allwinner,pins = "PI20", "PI21";
 				allwinner,function = "ps2";