[linux-sunxi] Problem with Allwinner H3 clocks
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From: Maxime Ripard <hidden>
Date: 2016-02-01 14:45:48
On Mon, Feb 01, 2016 at 10:37:45PM +0800, Chen-Yu Tsai wrote:
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There is, but it's opt-in, and we're not using it yet for anything but the hstimers (and in that case, we don't prevent the reclocking, we just take it into account).Shouldn't we be opt-ing in then ? At least the mmc driver makes clk_set_rate calls, it would be bad if that somehow ends up changing the pll6 rate while other peripherals are using it.The mod clocks do not have CLK_SET_RATE_PARENT set, which prevents the CCF from propagating clk_set_rate to its parent. As is for the other child clocks of PLL6. The only exception is the SATA clock in PLL6.
The PLL6 you're talking about is not the PLL6 we're talking about ;) We're talking about the A31's, while the SATA on the A10 / A20 is driven by the A10's (the equivalent for the A10 would be the PLL5) Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160201/3321040e/attachment.sig>