[linux-sunxi] Problem with Allwinner H3 clocks

On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:

On Thu, 28 Jan 2016 14:16:26 +0100
Jens Kuske [off-list ref] wrote:

quoted

after figuring out how to boot a devicetree kernel with allwinner's
u-boot I only had to add the mandatory
	
	clock-frequency = <24000000>;
	arm,cpu-registers-not-fw-configured;

to the timer node and v4.5-rc1 booted successfully. They are
intentionally left out in the official dt, because documentation says
one should prefer to fix the firmware -> mainline u-boot
No problems with clocks or uart here.

You are right, I had these lines in my DT. Thanks.

And even though you had these lines, it was still not working? Or is
it working now? I'm confused.

But, now, what about the PLL8 (periph1) which should be used by the MMCs?

I just sent another version of the pll6 rework to enable it.

The A23/A33/H3 (and surely some other SoCs) documentations about
the peripheral/periph/periph0/periph1 PLLs say:

	Note: The PLL Output should be fixed to 600MHz, it is not
	recommended to vary this value arbitrarily.

I don't know if it's worth it at this point. The pll6 seems to work
fine at other rates. Have you experienced any breakage when running at
another frequency?

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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