On 01/19, Loc Ho wrote:

Add X-Gene SoC and PMD PLL clocks support for v2 hardware.
X-Gene SoC v2 and above use an slightly different SoC
and PMD PLL hardware logic.

Signed-off-by: Loc Ho <redacted>
---

It's not from this patch, but I notice that we have a return
inside a void function in this file...

---8<---
From: Stephen Boyd <redacted>
Subject: [PATCH] clk: xgene: Remove return from void function

This function doesn't return anything because it's void. Drop the
return statement.

Cc: Loc Ho <redacted>
Signed-off-by: Stephen Boyd <redacted>
---
 drivers/clk/clk-xgene.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 266d573b9134..bd7156baa08b 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c

@@ -50,7 +50,7 @@ static inline u32 xgene_clk_read(void __iomem *csr)
 
 static inline void xgene_clk_write(u32 data, void __iomem *csr)
 {
-	return writel_relaxed(data, csr);
+	writel_relaxed(data, csr);
 }
 
 /* PLL Clock */

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