On Tue, Mar 17, 2015 at 04:17:48PM +0000, Russell King - ARM Linux wrote:

On Tue, Mar 17, 2015 at 03:51:53PM +0000, Sudeep Holla wrote:

quoted

That's bad. I started with 2 cycles for all(rd/wr/setup) latencies(data
and tag ram) and narrowed down to this setting with multiple
experiments. I did try booting 10 times each time at-least.

Since the bootmon sets 8 cycles for all the latencies, does it make
sense to try that setting to check if the issue you are seeing is
related to L2 latencies at all. Meanwhile I will continue my testing.

For me <2 2 1> works - so read and write latencies of 2, setup of 1.

So what's happening?  Is someone going to update the dtb to adjust the
latencies so that we can have a reliable platform?

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