Thread (14 messages) 14 messages, 3 authors, 2015-03-26
STALE4130d
Revisions (7)
  1. v1 [diff vs current]
  2. v2 [diff vs current]
  3. v2 [diff vs current]
  4. v2 [diff vs current]
  5. v1 [diff vs current]
  6. v5 current
  7. v5 [diff vs current]

[PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists

From: Alex Bennée <hidden>
Date: 2015-03-23 17:05:44
Also in: kvm, kvmarm, qemu-devel
Subsystem: the rest · Maintainer: Linus Torvalds

I was getting very confused about the duplication of state so wanted to
make it explicit.

Signed-off-by: Alex Benn?e <redacted>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211c..6dc1799 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
        This contains all the other bits.  Use cpsr_{read,write} to access
        the whole CPSR.  */
     uint32_t uncached_cpsr;
+    /* The spsr is a alias for spsr_elN where N is the current
+     * exception level. It is provided for here so the TCG msr/mrs
+     * implementation can access one register. Care needs to be taken
+     * to ensure the banked_spsr[] is also updated.
+     */
     uint32_t spsr;
 
     /* Banked registers.  */
-- 
2.3.2
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help