Thread (12 messages) flat view 12 messages, 4 authors, 2015-02-25

[PATCH 2/2] ARM: shmobile: r8a7794: add GPIO DT support

From: laurent.pinchart@ideasonboard.com (Laurent Pinchart)
Date: 2015-02-25 14:08:38
Also in: linux-devicetree, linux-sh

Hi Sergei,

On Wednesday 25 February 2015 17:04:53 Sergei Shtylyov wrote:
On 2/25/2015 1:11 PM, Laurent Pinchart wrote:
quoted
quoted
Describe GPIO[0-6] controllers in the R8A7794 device tree.

Based on original patch by Hisashi Nakamura
[off-list ref].

Signed-off-by: Sergei Shtylyov <redacted>

---

  arch/arm/boot/dts/r8a7794.dtsi |   84 +++++++++++++++++++++++++++++++++
  1 file changed, 84 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7794.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi
+++ renesas/arch/arm/boot/dts/r8a7794.dtsi
@@ -50,6 +50,90 @@
[...]
quoted
quoted
+	gpio1: gpio at e6051000 {
+		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
+		reg = <0 0xe6051000 0 0x50>;
+		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 32>;
This GPIO block has 26 GPIOs only.
[...]
quoted
quoted
+	gpio5: gpio at e6055000 {
+		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
+		reg = <0 0xe6055000 0 0x50>;
+		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 160 32>;
This GPIO block has 28 GPIOs only.
quoted
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
+	};
+
+	gpio6: gpio at e6055400 {
+		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
+		reg = <0 0xe6055400 0 0x50>;
+		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 192 32>;
This GPIO block has 26 GPIOs only.
Yes, I know; I just wasn't sure what to do with the "gpio-ranges" prop of
the following GPIO node. Should I keep the base GPIO # or update it as well?
I think the base number should be kept as-is, as the pfc driver indexes GPIOs 
using 32 * bank + offset. There are thus holes in the pfc pins array, but that 
shouldn't be a big deal (of course if you can find an easy way to optimize 
that, it would be welcome :-)).

-- 
Regards,

Laurent Pinchart
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