Hi Maxime,
Am Donnerstag, den 12.02.2015, 18:46 +0100 schrieb Maxime Coquelin:
[...]
+ soc {
+ reset_ahb1: reset at 40023810 {
+ #reset-cells = <1>;
+ compatible = "st,stm32-reset";
+ reg = <0x40023810 0x4>;
+ };
+
+ reset_ahb2: reset at 40023814 {
+ #reset-cells = <1>;
+ compatible = "st,stm32-reset";
+ reg = <0x40023814 0x4>;
+ };
+
+ reset_ahb3: reset at 40023818 {
+ #reset-cells = <1>;
+ compatible = "st,stm32-reset";
+ reg = <0x40023818 0x4>;
+ };
+
+ reset_apb1: reset at 40023820 {
+ #reset-cells = <1>;
+ compatible = "st,stm32-reset";
+ reg = <0x40023820 0x4>;
+ };
+
+ reset_apb2: reset at 40023824 {
+ #reset-cells = <1>;
+ compatible = "st,stm32-reset";
+ reg = <0x40023824 0x4>;
+ };
These are mostly consecutive, single registers. I wonder if these are
part of the same IP block and thus should be grouped together into the
same reset controller node?
regards
Philipp