Thread (18 messages) 18 messages, 5 authors, 2014-09-10

[PATCH v2 3/8] Documentation: bindings: net: add the Marvell PXA168 Ethernet controller

STALE4409d

From: Antoine Tenart <hidden>
Date: 2014-09-09 14:46:22
Also in: linux-devicetree, lkml, netdev
Subsystem: networking drivers, open firmware and flattened device tree bindings, the rest · Maintainers: Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds

Revision v2 of 6 in this series.

Revisions (6)
  1. v1 [diff vs current]
  2. v2 current
  3. v3 [diff vs current]
  4. v4 [diff vs current]
  5. v6 [diff vs current]
  6. v6 [diff vs current]
This adds the binding documentation for the Marvell PXA168 Ethernet
controller, following its DT support.

Signed-off-by: Antoine Tenart <redacted>
---
 .../devicetree/bindings/net/marvell-pxa168.txt     | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-pxa168.txt
diff --git a/Documentation/devicetree/bindings/net/marvell-pxa168.txt b/Documentation/devicetree/bindings/net/marvell-pxa168.txt
new file mode 100644
index 000000000000..3a5320ad09a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell-pxa168.txt
@@ -0,0 +1,22 @@
+* Marvell PXA168 Ethernet Controller
+
+Required properties:
+- compatible: should be "marvell,pxa168-eth".
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device.
+- clocks: pointer to the clock for the device.
+- clock-names: should be "MFUCLK".
+
+Optional properties:
+- port-id: should be '0','1' or '2'.
+- phy-addr: MDIO address of the PHY.
+
+Example:
+
+	eth0: ethernet at f7b90000 {
+		compatible = "marvell,pxa168-eth";
+		reg = <0xf7b90000 0x10000>;
+		clocks = <&chip CLKID_GETH0>;
+		clock-names = "MFUCLK";
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+	};
-- 
1.9.1
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