On 14.07.2014 15:38, Thomas Abraham wrote:

From: Thomas Abraham <redacted>

Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <redacted>
Signed-off-by: Thomas Abraham <redacted>
Reviewed-by: Amit Daniel Kachhap <redacted>
Tested-by: Arjun K.V <redacted>
---
 drivers/clk/samsung/clk-exynos5420.c |   28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

Looks good. Will apply.

Best regards,
Tomasz