On Mon, Jul 21, 2014 at 9:09 PM, Tuomas Tynkkynen [off-list ref] wrote:

Add a new cpufreq driver for Tegra124. Instead of using the PLLX as

<snip>

+
+static int tegra124_cpu_switch_to_dfll(void)
+{
+       struct clk *original_cpu_clk_parent;
+       unsigned long rate;
+       struct dev_pm_opp *opp;
+       int ret;
+
+       rate = clk_get_rate(cpu_clk);
+       opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
+       if (IS_ERR(opp))
+               return PTR_ERR(opp);
+
+       ret = clk_set_rate(dfll_clk, rate);
+       if (ret)
+               return ret;
+
+       original_cpu_clk_parent = clk_get_parent(cpu_clk);
+       clk_set_parent(cpu_clk, pllp_clk);

Needs return check.

+       if (ret)
+               return ret;

Which 'ret' is being checked here? nothing is assigned here. May be
fixing previous comment will fix this.

+
+       ret = clk_prepare_enable(dfll_clk);

<snip>

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-- 
Thanks and Regards
Pramod