[PATCH v2 10/16] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
STALE4429d
From: Tuomas Tynkkynen <hidden>
Date: 2014-07-21 15:42:39
Also in:
linux-devicetree, linux-pm, linux-tegra, lkml
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Prashant Gaikwad, Linus Torvalds
Revision v2 of 3 in this series.
Revisions (3)
- v1 [diff vs current]
- v2 current
- v4 [diff vs current]
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen <redacted>
---
v2 changes:
- none
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index feb3201..f1f4410 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c@@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", - "unused", "pll_x" }; + "unused", "pll_x", "unused", "unused", + "unused", "unused", "unused", "unused", + "dfllCPU_out" }; static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused",
--
1.8.1.5