[PATCH v2 2/4] ARM: imx: clk-vf610: fix FlexCAN clock gating
From: Shawn Guo <hidden>
Date: 2014-07-14 13:39:47
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Copy Jingchang ... On Mon, Jul 14, 2014 at 09:48:29AM +0200, Stefan Agner wrote:
quoted hunk ↗ jump to hunk
Extend the clock control for FlexCAN with the second gate which enable the clocks in the Clock Divider (CCM_CSCDR2) register too. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/mach-imx/clk-vf610.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index 22dc3ee..b12b888 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c@@ -295,8 +295,10 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); - clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); - clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_FLEXCAN0] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11); + clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0));
I do not quite understand what "flexcan0_en" clock is and the relationship between it and clock "flexcan0". I do not think it's a parent-child clock relationship. Jingchang, do you have more info on this? Also when you add a new clock, you should have a new clock ID, something like VF610_CLK_FLEXCAN0_EN. Shawn
+ clk[VF610_CLK_FLEXCAN1] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12);
+ clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4));
clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
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2.0.1