[PATCH 8/9] ARM: kernel: add support for cpu cache information
From: Stephen Boyd <hidden>
Date: 2014-06-26 00:19:15
Also in:
lkml
From: Stephen Boyd <hidden>
Date: 2014-06-26 00:19:15
Also in:
lkml
On 06/25/14 10:30, Sudeep Holla wrote:
+ +/* + * Which cache CCSIDR represents depends on CSSELR value + * Make sure no one else changes CSSELR during this + * smp_call_function_single prevents preemption for us + */
Where's the smp_call_function_single() or preemption disable happening?
+static inline u32 get_ccsidr(u32 csselr)
+{
+ u32 ccsidr;
+
+ /* Put value into CSSELR */
+ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+ isb();
+ /* Read result out of CCSIDR */
+ asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
+
+ return ccsidr;
+}
+-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation