Thread (14 messages) 14 messages, 3 authors, 2014-03-11

[PATCH 7/7] PCI: designware: split samsung and fsl bindings

From: arnd@arndb.de (Arnd Bergmann)
Date: 2014-03-04 14:53:39
Also in: linux-devicetree, linux-samsung-soc, linux-sh, linux-tegra

On Tuesday 04 March 2014, Lucas Stach wrote:
Right, we should be able to reuse the clock names. Though I'm not really
sure how the Samsung clocks maps to those used on i.MX, as the names are
a bit generic. Maybe someone from Samsung could shed a bit of light on
this.

On i.MX6 the clock names (which I have to agree are pretty bad) map as
follows:
pcie_axi: host controller main register/bus access clock
pcie_ref_125m: pcie phy reference clock

sata_ref_100m: pcie bus 100MHz reference clock
That doesn't explain why it's called "sata_ref_100m".
lvds_gate: bad abstraction. Decides if the reference clock is sourced
internal (i.e. the 100MHz ref clock above) or from an SoC external
source. We should really find a better way of representing this in the
clock tree.
I don't understand this description at all. Can you try to explain that
with different words?

	Arnd
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