Thread (14 messages) 14 messages, 3 authors, 2014-03-11

[PATCH 7/7] PCI: designware: split samsung and fsl bindings

From: arnd@arndb.de (Arnd Bergmann)
Date: 2014-02-28 20:03:01
Also in: linux-devicetree, linux-samsung-soc, linux-sh, linux-tegra

On Friday 28 February 2014, Lucas Stach wrote:
+Required properties:
+- compatible: "fsl,imx6q-pcie"
+- reg: base addresse and length of the pcie controller
+- interrupts: First entry must contain interrupt handle for controller
+  INTA output.
I think this should be documented as "optional" and only for
backwards compatibility with old kernels.
+- clocks: Must contain an entry for each entry in clock-names.
+       See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries: 
+       - "pcie_ref_125m"
+       - "sata_ref_100m"
+       - "lvds_gate"
+       - "pcie_axi"
I don't understand why you have completely different clocks here
from the exynos documentation. The clock names should really be
the same. Also, why do you have a "sata_ref_100m" clock?
Is this just driving a device that happens to be on-board
for a specific machine? Same for the "lvds_gate".

	Arnd
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