On Thursday, March 27, 2014 at 12:45:01 PM, Jingoo Han wrote:

On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:

quoted

In DRA7, the cpu sees 32bit address, but the pcie controller can see only
28bit address. So whenever the cpu issues a read/write request, the 4
most significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe
controller but the PCIe controller will see only (0x000_0000 -
0xFFF_FFF). So for programming the outbound translation window the
*base* should be programmed as 0x000_0000. Whenever we try to write to
say 0x2000_0000, it will be translated to whatever we have programmed in
the translation window with base as 0x000_0000.

Signed-off-by: Kishon Vijay Abraham I <redacted>

(+cc Pratyush Anand, Marek Vasut, Richard Zhu)

Thanks.

Acked-by: Jingoo Han <redacted>

This patch has no impact on MX6, the mask on MX6 is ~0 . A few comments below 
...
[...]

quoted

diff --git a/drivers/pci/host/pcie-designware.c

b/drivers/pci/host/pcie-designware.c index 17ce88f..98b661c 100644

--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c

@@ -464,6 +464,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)

 		return -EINVAL;
 	
 	}

+	if (of_property_read_u64(np, "base-mask", &pp->base_mask))
+		pp->base_mask = ~(0x0ULL);

You can just use ~0x0ULL without the () I believe.

[...]

quoted

diff --git a/drivers/pci/host/pcie-designware.h

b/drivers/pci/host/pcie-designware.h index 3063b35..3fa12a6 100644

--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h

@@ -35,6 +35,7 @@ struct pcie_port {

 	struct device		*dev;
 	u8			root_bus_nr;
 	void __iomem		*dbi_base;

+	u64			base_mask;

 	u64			cfg0_base;
 	void __iomem		*va_cfg0_base;
 	u64			cfg1_base;

This structure contains a lot of slop, check [1] please. We really should be 
more careful about the structures. I think a separate patch to clean this up 
would be fine though.

[1] http://www.catb.org/esr/structure-packing/