[PATCH v4 06/13] ARM: mvebu: Add a new set of registers for pmsu
From: Gregory CLEMENT <hidden>
Date: 2014-02-13 17:33:29
Also in:
linux-pm
Subsystem:
arm port, arm/marvell kirkwood and armada 370, 375, 38x, 39x, xp, 3700, 7k/8k, cn9130 soc support, the rest · Maintainers:
Russell King, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Linus Torvalds
The Power Management Unit Service block also controls the Coherency Fabric subsystem. This new set of registers is needed for the CPU idle implementation for the Armada 370/XP, it allows to enter a deep CPU idle state where the Coherency Fabric and the L2 cache are powered down. This patch also adds warnings if one of the base registers set can't be ioremapped. Signed-off-by: Gregory CLEMENT <redacted> --- arch/arm/mach-mvebu/pmsu.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index d71ef53107c4..aa5ef7439d0f 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c@@ -26,6 +26,7 @@ static void __iomem *pmsu_mp_base; static void __iomem *pmsu_reset_base; +static void __iomem *pmsu_fabric_base; #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x24) #define PMSU_RESET_CTL_OFFSET(cpu) (cpu * 0x8)
@@ -67,7 +68,11 @@ static int __init armada_370_xp_pmsu_init(void) if (np) { pr_info("Initializing Power Management Service Unit\n"); pmsu_mp_base = of_iomap(np, 0); + WARN_ON(!pmsu_mp_base); pmsu_reset_base = of_iomap(np, 1); + WARN_ON(!pmsu_reset_base); + pmsu_fabric_base = of_iomap(np, 2); + WARN_ON(!pmsu_fabric_base); of_node_put(np); }
--
1.8.1.2