[PATCH 0/4] clk: mvebu: fix clk init order
From: sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)
Date: 2014-01-30 10:31:39
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On 01/30/14 11:24, Gregory CLEMENT wrote:
On 25/01/2014 19:19, Sebastian Hesselbarth wrote:quoted
This patch set fixes clk init order that went upside-down with v3.14. I haven't really investigated what caused this, but I assume it is related with DT node reordering by addresses.Can you explain what kind of issue do you observe?
Sure. When probing CLK_OF_DECLAREed clock drivers, clock-gating driver gets registered before core-clocks. It therefore cannot resolve it's parent clock name for tclk and all clock gates will have no parent clock. Usually, you'll see in some drivers (e.g. v643xx_eth) div_by_zero errors poping up, when they calculate a frequency division factors based on clock gate frequency, which should have been tclk but is 0 now.
I have just tested the master branch of Linus and (excepted for SATA but Andrew will send a patch set soon), I didn't experiment any issues on Armada 370 and Armada XP based boards.