[PATCH 06/11] pinctrl: mvebu: dove: request additional resources
From: sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)
Date: 2014-01-25 18:37:31
Also in:
lkml
Subsystem:
arm/marvell kirkwood and armada 370, 375, 38x, 39x, xp, 3700, 7k/8k, cn9130 soc support, pin control subsystem, the rest · Maintainers:
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Linus Walleij, Linus Torvalds
Dove pinctrl also requires additional registers to control all pins. This patch requests resources for mpp4 and pmu-mpp register ranges. As this changes DT to driver requirements, fallback to hardcoded resources, if the corresponding DT regs have not been set. Also, WARN about old DT binding usage to encourage users to update their DTBs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- Cc: Jason Cooper <redacted> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <redacted> Cc: Linus Walleij <redacted> Cc: linux-arm-kernel at lists.infradead.org Cc: linux-kernel at vger.kernel.org --- drivers/pinctrl/mvebu/pinctrl-dove.c | 52 +++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index f4141e60a52b..3f34975c441f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c@@ -22,6 +22,11 @@ #include "pinctrl-mvebu.h" +/* Internal registers can be configured at any 1 MiB aligned address */ +#define INT_REGS_MASK ~(SZ_1M - 1) +#define MPP4_REGS_OFFS 0xd0440 +#define PMU_REGS_OFFS 0xd802c + #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
@@ -55,6 +60,10 @@ #define CONFIG_PMU BIT(4) +static void __iomem *mpp_base; +static void __iomem *mpp4_base; +static void __iomem *pmu_base; + static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl, unsigned long *config) {
@@ -776,13 +785,42 @@ static int dove_pinctrl_probe(struct platform_device *pdev) { const struct of_device_id *match = of_match_device(dove_pinctrl_of_match, &pdev->dev); - struct resource *res; - void __iomem *base; + struct resource *mpp_res, *res; + struct resource res_fallback; + + mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); + if (IS_ERR(mpp_base)) + return PTR_ERR(mpp_base); + + /* prepare fallback resource */ + memcpy(&res_fallback, mpp_res, sizeof(struct resource)); + res_fallback.start = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n"); + adjust_resource(&res_fallback, + (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4); + res = &res_fallback; + } + mpp4_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mpp4_base)) + return PTR_ERR(mpp4_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) { + dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n"); + adjust_resource(&res_fallback, + (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8); + res = &res_fallback; + } + pmu_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pmu_base)) + return PTR_ERR(pmu_base); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + /* Warn on any missing DT resource */ + WARN(res_fallback.start, "Missing pinctrl regs in DTB. Please update your firmware.\n"); pdev->dev.platform_data = (void *)match->data;
@@ -797,7 +835,7 @@ static int dove_pinctrl_probe(struct platform_device *pdev) } clk_prepare_enable(clk); - return mvebu_pinctrl_probe(pdev, base); + return mvebu_pinctrl_probe(pdev, mpp_base); } static int dove_pinctrl_remove(struct platform_device *pdev)
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1.8.5.2