[PATCH] ARM: cache-v7: Disable preemption when reading CCSIDR
From: nico@fluxnic.net (Nicolas Pitre)
Date: 2012-02-14 17:30:04
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On Tue, 14 Feb 2012, Rabin Vincent wrote:
On Mon, Feb 13, 2012 at 11:29:01PM +0000, Russell King - ARM Linux wrote:quoted
On Mon, Feb 13, 2012 at 02:23:29PM -0800, Stephen Boyd wrote:quoted
On 02/13/12 10:15, Russell King - ARM Linux wrote:quoted
On Mon, Feb 13, 2012 at 10:13:27AM -0800, Stephen Boyd wrote:quoted
Thanks. Russell has already merged the original patch to the fixes branch. Hopefully he can fold this one in.Nope, I've asked Linus to pull it. So do we conclude that the original patch wasn't properly tested? :PSigh. Lockdep strikes again! I promise I tested it with lockdep disabled. It looks like Linus' hasn't pulled yet but maybe he just hasn't published it.It's not nice to change something after you've sent a pull request - there's no way of knowing when Linus actually pulls it before he's published it, and if he gets something different then it can raise questions. So, it's gone in as-is, and, as I'm now intending asking for another pull request soo soon after my previous one, this is something that we will have to live with probably for the remainder of the week.OK, since it can't be folded in, here is a proper patch: 8<---------quoted
From 26f02624a20a61ed1997a4e8648e4c766a54d91d Mon Sep 17 00:00:00 2001From: Rabin Vincent <redacted> Date: Tue, 14 Feb 2012 19:22:07 +0530 Subject: [PATCH] ARM: fix v7 boot with lockdep enabled Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Cc: Stephen Boyd <redacted> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Nicolas Pitre <redacted>
Reviewed-by: Nicolas Pitre <redacted>
quoted hunk ↗ jump to hunk
Cc: stable at vger.kernel.org Signed-off-by: Rabin Vincent <redacted> --- arch/arm/include/asm/assembler.h | 5 +++++ arch/arm/mm/cache-v7.S | 2 +- 2 files changed, 6 insertions(+), 1 deletions(-)diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 62f8095..23371b1 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h@@ -137,6 +137,11 @@ disable_irq .endm + .macro save_and_disable_irqs_notrace, oldcpsr + mrs \oldcpsr, cpsr + disable_irq_notrace + .endm + /* * Restore interrupt state previously stored in a register. We don't * guarantee that this will preserve the flags.diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7a24d396..a655d3d 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S@@ -55,7 +55,7 @@ loop1: cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache #ifdef CONFIG_PREEMPT - save_and_disable_irqs r9 @ make cssr&csidr read atomic + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr-- 1.7.9