[PATCH v2 1/2] dmaengine: Add support for per xfer specific privatedata & box dma
From: Ravi Kumar V <hidden>
Date: 2012-01-06 12:48:12
Also in:
linux-arch, linux-arm-msm, lkml
Subsystem:
dma generic offload engine subsystem, generic include/asm header files, the rest · Maintainers:
Vinod Koul, Arnd Bergmann, Linus Torvalds
Qualcomm MSM have a feature to pass command configuration and control data along with source,destination and length of transfer for every transaction, as of now struct scatterlist has no support to send private data related to each transaction we added private_data variable for supporting this type of archictures. Qualcomm MSM also supports BOX mode of dma, currently as there is no API in dmaengine to support this type of dma we added new API. Change-Id: Ia9ee19f2c253e68b8e5ff254a57478dcc51014ca Signed-off-by: Ravi Kumar V <redacted> --- include/asm-generic/scatterlist.h | 1 + include/linux/dmaengine.h | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/include/asm-generic/scatterlist.h b/include/asm-generic/scatterlist.h
index 5de0735..e66dfcb 100644
--- a/include/asm-generic/scatterlist.h
+++ b/include/asm-generic/scatterlist.h@@ -14,6 +14,7 @@ struct scatterlist { #ifdef CONFIG_NEED_SG_DMA_LENGTH unsigned int dma_length; #endif + unsigned long private_data; }; /*
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 75f53f8..ea29e73 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h@@ -72,10 +72,11 @@ enum dma_transaction_type { DMA_ASYNC_TX, DMA_SLAVE, DMA_CYCLIC, + DMA_BOX, }; /* last transaction type for creation of the capabilities mask */ -#define DMA_TX_TYPE_END (DMA_CYCLIC + 1) +#define DMA_TX_TYPE_END (DMA_BOX + 1) /**
@@ -404,6 +405,15 @@ struct dma_tx_state { u32 residue; }; + +struct dma_box_list { + dma_addr_t dma_row_address; + unsigned int dma_row_len; + unsigned int dma_row_num; + unsigned int dma_row_offset; + unsigned long private_data; +}; + /** * struct dma_device - info on the entity supplying DMA services * @chancnt: how many DMA channels are supported
@@ -497,6 +507,11 @@ struct dma_device { struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_data_direction direction); + struct dma_async_tx_descriptor *(*device_prep_dma_box)( + struct dma_chan *chan, struct dma_box_list *dst_box, + struct dma_box_list *src_box, unsigned int num_list, + unsigned long flags); + int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg);
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.