[PATCH v7 09/16] ARM: LPAE: MMU setup for the 3-level page table format

On Fri, 2011-08-19 at 12:10 +0100, Catalin Marinas wrote:

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+ */
+ENTRY(cpu_v7_set_pte_ext)
+#ifdef CONFIG_MMU
+       tst     r2, #L_PTE_PRESENT
+       beq     1f
+       tst     r3, #1 << (55 - 32)             @ L_PTE_DIRTY
+       orreq   r2, #L_PTE_RDONLY
+1:     strd    r2, r3, [r0]

AIUI this 64-bit store is not atomic. Is there something about the

ARM

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architecture which would prevent the MMU prefetching the half

written

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entry and caching it in the TLB?

CPU implementations that include LPAE guarantee the atomicity of a
double-word store (STRD) if the alignment is correct. 

Ah, I was looking at the standard v7 docs and not the LPAE extensions, I
see it now.

Thanks,
Ian.

-- 
Ian Campbell

The disks are getting full; purge a file today.