On Mon, Jun 27, 2011 at 2:02 PM, Russell King - ARM Linux
[off-list ref] wrote:

On Mon, Jun 27, 2011 at 01:34:48PM +0300, saeed bishara wrote:

quoted

Russell,
? I'm curious about the correctness of this patch for systems with
outer cache. shouldn't the dsb be issued before the outer cache
maintenance?

Maybe we should do two passes over SG lists then - one for the inner and
another for the outer cache?

In effect we could do three passes:

1. Calculate the total size of the SG list to determine whether full
? cache flush is more efficient.
2. Flush inner cache
? Then dsb()
3. Flush outer cache
? Another dsb()

looking at l2x0 cache, it seems to me that it would be possible to do
asynchronous l2 cache maintenance for
range operations, so maybe that can be utilized in order to
parallelism between inner cache and outer cache maintenance,
so the flow can be:
2. Flush sg buffer from inner cache
3. dsb()
4. start Flush outer cache for that buffer
5. Flush next sg buffer from inner cache
6. dsb
7. goto 4.
8. when no more buffers left, wait for outer cache operations

saeed