[PATCH 05/10] clk: Add support for simple dividers

On Thu, Apr 28, 2011 at 04:22:17PM +0100, Russell King - ARM Linux wrote:

On Mon, Apr 18, 2011 at 11:49:09AM +0200, Uwe Kleine-K?nig wrote:

quoted

quoted

+static int clk_divider_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long best_parent_rate;
+	struct clk_divider *divider = to_clk_divider(clk);
+	unsigned int div;
+	int ret;
+	unsigned long flags = 0;
+	u32 val;
+
+	div = clk_divider_bestdiv(clk, rate, &best_parent_rate);
+
+	if (rate != best_parent_rate / div)
+		return -EINVAL;

This is too harsh, isn't it. Or can you expect to only get values that
are returned by round_rate? Again you need DIV_ROUND_UP.

It is too harsh, and I've wished many a time that people would implement
clk_set_rate() and clk_round_rate() as:

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	err = calculate_clock_paramters(clk, params, rate);
	if (err < 0)
		return err;
	return calculate_clock_rate(clk, params);
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	err = calculate_clock_parameters(clk, params, rate);
	if (err < 0)
		return err;
	set_clock_parameters(clk, params);
	clk->rate = calculate_clock_rate(clk, params);
	return 0;
}

IOW, clk_round_rate() does what clk_set_rate() does but does _not_ set
the hardware rate itself.

Ok. It's easier to implement anyway since rounding errors do not have
such a bad impact.

Sascha


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