[PATCH] ARM: errata: pl310 cache sync operation may be faulty

On Tue, Feb 15, 2011 at 12:34:22 +0100, Russell King - ARM Linux wrote:

On Tue, Feb 15, 2011 at 04:48:03PM +0530, srinidhi kasagar wrote:

quoted

+#ifdef ARM_ERRATA_753970
+#define L2X0_DUMMY_REG  0x740
+	/* write to an unmmapped register */
+	writel_relaxed(0, base + L2X0_DUMMY_REG);
+	cache_wait(base + L2X0_CACHE_SYNC, 1);
+#else
 	writel_relaxed(0, base + L2X0_CACHE_SYNC);
 	cache_wait(base + L2X0_CACHE_SYNC, 1);
+#endif

So why wrap cache_wait() up in that horrible ifdef as well - and why not
put the dummy register definition along side the other register definitions?

OK. In fact cache_wait need not have to be under ifdef
as this bug found only on PL310 where the sync operations
are atomic. I will send out a new patch.

srinidhi