The effect of cache sync operation is to drain the store
buffer and wait for all internal buffers to be empty. In
normal conditions, store buffer is able to merge the
normal memory writes within its 32-byte data buffers.
Due to this erratum present in r3p0, the effect of cache
sync operation on the store buffer still remains when
the operation completes. This means that the store buffer
is always asked to drain and this prevents it from merging
any further writes.
This can severely affect performance on the write traffic
esp. on Normal memory NC one.
The proposed workaround is to replace the normal offset of
cache sync operation(0x730) by another offset targeting an
unmapped PL310 register 0x740.
Signed-off-by: srinidhi kasagar <redacted>
Acked-by: Linus Walleij <redacted>
---
arch/arm/Kconfig | 15 +++++++++++++++
arch/arm/mm/cache-l2x0.c | 8 ++++++++
2 files changed, 23 insertions(+), 0 deletions(-)
On 15 February 2011 11:18, srinidhi kasagar
[off-list ref] wrote:
+config ARM_ERRATA_753970
+ ? ? ? bool "ARM errata: cache sync operation may be faulty"
+ ? ? ? depends on CACHE_PL310
+ ? ? ? help
+ ? ? ? ? This option enables the workaround for the 753970 PL310 erratum.
Is this number correct? I couldn't find it in ARM's internal database.
+ ? ? ? ? Under some condition the effect of cache sync operation on
+ ? ? ? ? the store buffer still remains when the operation completes.
+ ? ? ? ? This means that the store buffer is always asked to drain and
+ ? ? ? ? this prevents it from merging any further writes. The workaround
+ ? ? ? ? is to replace the normal offset of cache sync operation (0x730)
+ ? ? ? ? by another offset targeting an unmapped PL310 register 0x740.
+ ? ? ? ? This has the same effect as the cache sync operation: store buffer
+ ? ? ? ? drain and waiting for all buffers empty.
You may want to specify the revision number this applies to so that
people to enable it if not needed.
--
Catalin
On Tue, Feb 15, 2011 at 17:38:52 +0100, Catalin Marinas wrote:
On 15 February 2011 11:18, srinidhi kasagar
[off-list ref] wrote:
quoted
+config ARM_ERRATA_753970
+ ? ? ? bool "ARM errata: cache sync operation may be faulty"
+ ? ? ? depends on CACHE_PL310
+ ? ? ? help
+ ? ? ? ? This option enables the workaround for the 753970 PL310 erratum.
Is this number correct? I couldn't find it in ARM's internal database.
yes, we got this errata notice from ARM recently (10-feb-11), document
revision 12.1
quoted
+ ? ? ? ? Under some condition the effect of cache sync operation on
+ ? ? ? ? the store buffer still remains when the operation completes.
+ ? ? ? ? This means that the store buffer is always asked to drain and
+ ? ? ? ? this prevents it from merging any further writes. The workaround
+ ? ? ? ? is to replace the normal offset of cache sync operation (0x730)
+ ? ? ? ? by another offset targeting an unmapped PL310 register 0x740.
+ ? ? ? ? This has the same effect as the cache sync operation: store buffer
+ ? ? ? ? drain and waiting for all buffers empty.
You may want to specify the revision number this applies to so that
people to enable it if not needed.
On Tue, Feb 15, 2011 at 12:34:22 +0100, Russell King - ARM Linux wrote:
On Tue, Feb 15, 2011 at 04:48:03PM +0530, srinidhi kasagar wrote:
quoted
+#ifdef ARM_ERRATA_753970
+#define L2X0_DUMMY_REG 0x740
+ /* write to an unmmapped register */
+ writel_relaxed(0, base + L2X0_DUMMY_REG);
+ cache_wait(base + L2X0_CACHE_SYNC, 1);
+#else
writel_relaxed(0, base + L2X0_CACHE_SYNC);
cache_wait(base + L2X0_CACHE_SYNC, 1);
+#endif
So why wrap cache_wait() up in that horrible ifdef as well - and why not
put the dummy register definition along side the other register definitions?
OK. In fact cache_wait need not have to be under ifdef
as this bug found only on PL310 where the sync operations
are atomic. I will send out a new patch.
srinidhi
On Wed, 2011-02-16 at 05:08 +0000, Srinidhi KASAGAR wrote:
On Tue, Feb 15, 2011 at 17:38:52 +0100, Catalin Marinas wrote:
quoted
On 15 February 2011 11:18, srinidhi kasagar
[off-list ref] wrote:
quoted
+config ARM_ERRATA_753970
+ bool "ARM errata: cache sync operation may be faulty"
+ depends on CACHE_PL310
+ help
+ This option enables the workaround for the 753970 PL310 erratum.
Is this number correct? I couldn't find it in ARM's internal database.
yes, we got this errata notice from ARM recently (10-feb-11), document
revision 12.1
Ah, I found it (I was looking in the wrong place).
Catalin
You could still leave cache_wait() after #endif, even though it is a
no-op. I think it is clearer that the erratum workaround only targets
the sync.
--
Catalin
On Wed, 2011-02-16 at 12:34 +0000, Srinidhi KASAGAR wrote:
From 7a1fa2f8ec106bda4f940f5c9478ec16b2de6846 Mon Sep 17 00:00:00 2001
From: srinidhi kasagar <redacted>
Date: Mon, 14 Feb 2011 17:07:06 +0530
Subject: [PATCH] ARM: errata: pl310 cache sync operation may be faulty
The effect of cache sync operation is to drain the store
buffer and wait for all internal buffers to be empty. In
normal conditions, store buffer is able to merge the
normal memory writes within its 32-byte data buffers.
Due to this erratum present in r3p0, the effect of cache
sync operation on the store buffer still remains when
the operation completes. This means that the store buffer
is always asked to drain and this prevents it from merging
any further writes.
This can severely affect performance on the write traffic
esp. on Normal memory NC one.
The proposed workaround is to replace the normal offset of
cache sync operation(0x730) by another offset targeting an
unmapped PL310 register 0x740.
Signed-off-by: srinidhi kasagar <redacted>
Acked-by: Linus Walleij <redacted>