There are two types of bitfield definition in qspinlock data structues:

     * When NR_CPUS < 16K
     *  0- 7: locked byte
     *     8: pending
     *  9-15: not used
     * 16-17: tail index
     * 18-31: tail cpu (+1)
     *
     * When NR_CPUS >= 16K
     *  0- 7: locked byte
     *     8: pending
     *  9-10: tail index
     * 11-31: tail cpu (+1)

_Q_PENDING_BITS is 8 or 1 for the two types respectively. The second
type is a universal definition while the first type is an optimization
for NR_CPUS < 16K, but it relies on hardware 16bit xchg/cmpxchg support.

Unfortunately, some architectures don't have hardware sub-word xchg/
cmpxchg support. Though these archs can use software emulation (e.g.,
MIPS), but the cost is too expensive, and they have no benefits from
_Q_PENDING_BITS=8. So we only allow archs with ARCH_HAS_HW_XCHG_SMALL
to select _Q_PENDING_BITS=8.

This patch can let CSKY, RISC-V and other similar archs use qspinlock to
replace existing ticket spinlock.

Signed-off-by: Huacai Chen <redacted>
---
 include/asm-generic/qspinlock_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/asm-generic/qspinlock_types.h b/include/asm-generic/qspinlock_types.h
index 2fd1fb89ec36..458e5d941c92 100644
--- a/include/asm-generic/qspinlock_types.h
+++ b/include/asm-generic/qspinlock_types.h

@@ -71,7 +71,7 @@ typedef struct qspinlock {
 #define _Q_LOCKED_MASK		_Q_SET_MASK(LOCKED)
 
 #define _Q_PENDING_OFFSET	(_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
-#if CONFIG_NR_CPUS < (1U << 14)
+#if (CONFIG_NR_CPUS < (1U << 14)) && defined(CONFIG_ARCH_HAS_HW_XCHG_SMALL)
 #define _Q_PENDING_BITS		8
 #else
 #define _Q_PENDING_BITS		1

-- 
2.27.0