[PATCH v26 3/9] x86/cet/ibt: Handle signals for Indirect Branch Tracking
From: Yu-cheng Yu <hidden>
Date: 2021-04-27 20:48:18
Also in:
linux-arch, linux-doc, linux-mm, lkml
Subsystem:
the rest, x86 architecture (32-bit and 64-bit) · Maintainers:
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen
When an indirect CALL/JMP instruction is executed and before it reaches the target, it is in 'WAIT_ENDBR' status, which can be read from MSR_IA32_U_CET. The status is part of a task's status before a signal is raised and preserved in the signal frame. It is restored for sigreturn. IBT state machine is described in Intel SDM Vol. 1, Sec. 18.3. Signed-off-by: Yu-cheng Yu <redacted> Cc: Kees Cook <redacted> --- v25: - Move the addition of sc_ext.wait_endbr from an earlier shadow stack patch to here. - Change X86_FEATURE_CET to X86_FEATURE_SHSTK. - Change wrmsrl() to wrmsrl_safe() and handle error. v24: - Update for changes from splitting shadow stack and ibt. arch/x86/include/uapi/asm/sigcontext.h | 1 + arch/x86/kernel/fpu/signal.c | 33 +++++++++++++++++++++++--- 2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/uapi/asm/sigcontext.h b/arch/x86/include/uapi/asm/sigcontext.h
index 10d7fa192d48..ee5bacce7d87 100644
--- a/arch/x86/include/uapi/asm/sigcontext.h
+++ b/arch/x86/include/uapi/asm/sigcontext.h@@ -203,6 +203,7 @@ struct _xstate { struct sc_ext { unsigned long total_size; unsigned long ssp; + unsigned long wait_endbr; }; /*
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
index 0488407bec81..0ed01e70b09e 100644
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c@@ -71,16 +71,29 @@ int save_extra_state_to_sigframe(int ia32, void __user *fp, void __user *restore return err; ext.ssp = token_addr; + } + if (new_ssp || cet->ibt_enabled) { fpregs_lock(); if (test_thread_flag(TIF_NEED_FPU_LOAD)) __fpregs_load_activate(); if (new_ssp) err = wrmsrl_safe(MSR_IA32_PL3_SSP, new_ssp); + + if (!err && cet->ibt_enabled) { + u64 msr_val; + + err = rdmsrl_safe(MSR_IA32_U_CET, &msr_val); + if (!err && (msr_val & CET_WAIT_ENDBR)) { + ext.wait_endbr = 1; + msr_val &= ~CET_WAIT_ENDBR; + err = wrmsrl_safe(MSR_IA32_U_CET, msr_val); + } + } fpregs_unlock(); } - if (!err && ext.ssp) { + if (!err && (ext.ssp || cet->ibt_enabled)) { void __user *p = fp; ext.total_size = sizeof(ext);
@@ -110,7 +123,8 @@ static int get_extra_state_from_sigframe(int ia32, void __user *fp, struct sc_ex if (!cpu_feature_enabled(X86_FEATURE_SHSTK)) return 0; - if (!cet->shstk_size) + if (!cet->shstk_size && + !cet->ibt_enabled) return 0; memset(ext, 0, sizeof(*ext));
@@ -149,6 +163,19 @@ static int restore_extra_state_to_xregs(struct sc_ext *sc_ext) if (cet->shstk_size) err = wrmsrl_safe(MSR_IA32_PL3_SSP, sc_ext->ssp); + + if (err) + return err; + + if (cet->ibt_enabled && sc_ext->wait_endbr) { + u64 msr_val; + + err = rdmsrl_safe(MSR_IA32_U_CET, &msr_val); + if (!err) { + msr_val |= CET_WAIT_ENDBR; + err = wrmsrl_safe(MSR_IA32_U_CET, msr_val); + } + } #endif return err; }
@@ -616,7 +643,7 @@ static unsigned long fpu__alloc_sigcontext_ext(unsigned long sp) * sigcontext_ext is at: fpu + fpu_user_xstate_size + * FP_XSTATE_MAGIC2_SIZE, then aligned to 8. */ - if (cet->shstk_size) + if (cet->shstk_size || cet->ibt_enabled) sp -= (sizeof(struct sc_ext) + 8); #endif return sp;
--
2.21.0