Re: [NEEDS-REVIEW] [PATCH v15 03/26] x86/fpu/xstate: Introduce CET MSR XSAVES supervisor states

On 11/30/2020 9:45 AM, Dave Hansen wrote:

On 11/10/20 8:21 AM, Yu-cheng Yu wrote:

quoted

Control-flow Enforcement Technology (CET) adds five MSRs.  Introduce
them and their XSAVES supervisor states:

     MSR_IA32_U_CET (user-mode CET settings),
     MSR_IA32_PL3_SSP (user-mode Shadow Stack pointer),
     MSR_IA32_PL0_SSP (kernel-mode Shadow Stack pointer),
     MSR_IA32_PL1_SSP (Privilege Level 1 Shadow Stack pointer),
     MSR_IA32_PL2_SSP (Privilege Level 2 Shadow Stack pointer).

This patch goes into a bunch of XSAVE work that this changelog only
briefly touches on.  I think it needs to be beefed up a bit.

[...]

Do we have any other spots in the kernel where we care about:

	boot_cpu_has(X86_FEATURE_SHSTK) ||
	boot_cpu_has(X86_FEATURE_IBT)

?  If so, we could also address this by declaring a software-defined
X86_FEATURE_CET and then setting it if SHSTK||IBT is supported, then we
just put that one feature in xsave_cpuid_features[].

These features have different CPUIDs but are complementary parts.  I 
don't know if someday there will be shadow-stack-only CPUs, but an 
IBT-only CPU is weird.  What if the kernel checks that the CPU has both 
features and presents only one feature flag (X86_FEATURE_CET), no 
X86_FEATURE_SHSTK or X86_FEATURE_IBT?